The present disclosure is generally directed to addressing replicated bus units and, more particularly, to techniques for addressing topology specific replicated bus units in a data processing system. Topology specific replicated bus units (TSRBUs) are typically functional units replicated across a data processing system, possibly at varying levels of the interconnect hierarchy, with each TSRBU interacting with a specific subset of processors within the system. A commonly occurring TSRBU is an interrupt controller.
In computing, an interrupt controller is a device that is used to combine several interrupt sources on one or more processor core lines, while allowing priority levels to be assigned to interrupt outputs. Interrupt controllers typically have a common set of registers (e.g., an interrupt request register (IRR), an in-service register (ISR), and an interrupt mask register (IMR). The IRR specifies which interrupts are pending acknowledgement and is typically a symbolic register that cannot be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an end of interrupt (EOI) signal. The IMR specifies which interrupts are to be ignored and not acknowledged. In general, an interrupt controller may have up to two distinct interrupt requests outstanding at one time (e.g., one interrupt request waiting for acknowledgement, and one interrupt request waiting for an EOI). An interrupt controller may implement hard priorities, specific priorities, or rotating priorities and interrupts may be edge-triggered or level-triggered.
Addressing a TSRBU, e.g., an interrupt controller, has conventionally employed a unique address for each TSRBU in a data processing system. Given that each TSRBU has required software to utilize a different address to communicate with the TSRBU as the software is moved from one processor core to another processor core, user level software has conventionally been required to communicate indirectly with a TSRBU via system control software such as a hypervisor or operating system (OS). Requiring software to utilize a different address to communicate with different TSRBUs through system control software increases operating complexity.